Intel’s trend of increasingly less credible press releases accelerated yesterday when they “Unveiled” an FPGA with HBM2 memory. SemiAccurate spent the last 12 hours or so digging into this and the more we dug, the less truth we found.
Are Any Tweets Honest?:
It all started with a tweet about this press release which Intel once again seems to have neglected to send to the press, or at least the press they know are not tame. Now the wording seem to be a bit vague, “Intel Unveils” does not say Intel is shipping or Intel has functional products, just that they are unveiling it. The problem is the wording after unveils in the release, specifically, “Industry’s First FPGA Integrated With High Bandwidth Memory”. Why is this an issue?
Well to start out with they aren’t the first to unveil an FPGA with integrated high bandwidth memory, Xilinx was. Better yet they unveiled it over a year ago, see here for the exact release. What was now clear was that Intel was very likely doing something that a 3rd grade teacher would send children to a corner for attempting. That said SemiAccurate did something that few other sites bother with now, we asked Intel about it.
We said, with links cut out for formatting sanity, “Intel claims they are the first with an FPGA bearing HBM memory (link), Xilinx has one on the market and has had it for years: (link), Can I get a comment on how you can claim this? It will likely be for a story. Thanks.” Intel politely responded that they were going to get me to the right people for a response. Rather than a response, Intel published comments on Twitter that undercut our question before they responded to SemiAccurate. How ethical. In fact they didn’t respond until SemiAccurate pointed this behavior out.
Wording Is Important:
Intel’s eventual response had two parts, the first was, “The link you sent is a link to a product page where they announced that they will have a HBM-based product. We also had a general product announcement much earlier like theirs (In mid 2016), and the technical content has been on our website.” [Bold emphasis in original provided by Intel.] Second was a response that I am supposed to attribute to Jordon Inkeles, so I am. They said, “The news is that we are making available the FPGA+DRAM in a single package and customers can book it today, and select customers have it.”
Lets take a look at what they are saying in detail, followed by a distillation of some of the things SemiAccurate found out in the last 12 hours or so of calls and emails. The wording Intel used is painfully parsed, whichever team of lawyers Intel used to craft that possibly technically correct wording should get a raise. That said they missed a few big bits.
“The link you sent is a link to a product page where they announced that they will have a HBM-based product.” Yup, that is dead on true, Xilinx did NOT say they have ‘shipping product now’, more on what we found out on this front later. “We also had a general product announcement much earlier like theirs (In mid 2016), and the technical content has been on our website.” Intel helpfully did not provide a link to said release.
As usual we searched Intel’s site for a release about FPGAs and HBM. On the Intel Newsroom if you do a search for FPGA HBM, you get 41 news releases including yesterday’s, 8 editorials, and 16 News Bytes. The number that reference HBM in the article? One. That includes yesterday’s release. We can’t find anything that references the earlier release of FPGAs and HBM like Intel claimed, if you can please write the author and we will update.
We literally opened every article that seemed remotely relevant and did a keyword search for HBM and got nothing. We would ask Intel about this but given their ethical behavior last time we went to them with a serious question, we will ask AFTER publication this time and update if necessary. As far as we can tell Intel didn’t release anything before Xilinx did, but that doesn’t stop the claim. Maybe that call for a raise for the lawyers was premature. They were right that Xilinx did say “will have”, so kudos there for pointing out the obvious even if the bolding was a tad gauche.
The second quote is where things get interesting. “The news is that we are making available the FPGA+DRAM in a single package and customers can book it today, and select customers have it.” Why? A few reasons, wording mainly. “Making available” is not shipping, not by a long shot, and Intel is not shipping FPGA modules with HBM, at least not to anyone SemiAccurate talked to yesterday, but again more on this nuance later. Also not the use of “FPGA+DRAM in a single package”, specifically the word DRAM. Shouldn’t they have said HBM in light of the conversation? We found a lot more about this too, but again that is for later.
The last parts are pretty telling and show that they are not actually shipping it an FPGA with HBM and aren’t really close to doing so. Why do we say this? “Customers can book it today“. Fair enough, but what is the lead time again? If it was anything relatively near term we would almost assuredly have gotten a date, or at least a quarter. I can book orders right now for the 3nm FPGA with stacked memory that goes 15 inches high that I am drawing on toilet paper with crayons in the ‘reading room’ to avoid boredom. Book now, it will ship by Q2/2377 if all goes well. Intel not giving even a hint of a date on the booking tells all.
Then there is the part about, “select customers have it“. SemiAccurate called a lot of people on this topic. SemiAccurate emailed a lot of people on this topic. We got answers. We couldn’t find a single one that had a Stratix 10 MX FPGA with HBM memory, once again more details later. One way to parse the complete sentence Intel gave us, which does swing the lawyers back to the bonus territory, is, “We are shipping Stratix 10 SKUs that have some kind of memory on the package. You can order them now with no near term deliveries and some customers have Stratix 10 parts now but not ones with HBM.”
How Real Is Real?:
Since you can’t prove a negative we can’t be sure that Intel is not shipping Stratix 10’s with HBM, or at least sampling them, but the technical bits we found out strongly suggest the HBM variants don’t exist much less are leaving Intel’s labs at the moment. Why do we say this? Lets start out with the anecdotal evidence, the pictures of the parts Intel provided. Notice anything?
Precious is Shiny
If you took this picture to be the real Stratix 10 MX with HBM, it is clear Intel has made major advances with their 14nm technology on the shiny package front. If you aren’t as cynical and snarky as SemiAccurate, you might laugh at the 3rd rate photoshop job Intel did to fake their FPGA module. Come on guys, are you really this bad? Looking at the recent “5G” modem “pictures”, you would have to say no, they are much worse. See?
Yes they seriously sent this out as ‘real’
So Intel doesn’t have physical chips they can take pictures of. Doesn’t that say a lot about the status of these supposedly bookable parts? Do you think the ones customer “have” are real or CAD models? Chocolate for the holidays perhaps? If so I want a box of them! Actually this is one area that SemiAccurate did dig up a lot of information on, specifically what Intel _is_ actually shipping, and they are shipping Stratix 10’s at the moment. First though it helps to look at some of the tech.
Intel Won’t Talk Tech Anymore:
Intel/Altera’s Stratix 10 is the first FPGA shipping on Intel’s 14nm process. Customers have them and SemiAccurate has word that they feel the Stratix 10 is a hot product. We meant that literally, it isn’t living up to the reputation of non-Intel fabbed Altera FPGAs which are not such a hot, temperature-wise, product. It might have something to do with what SemiAccurate has been saying since mid-2014 about the process, it leaks like a sieve for certain types of functional units. FPGAs seem to be one of those types.
That said customers do have Stratix 10’s, specifically the 2800 line. This line is said by our moles to be the exact same part in the MX with HBM line, so the chips really exist at this point. The problem seems to be in the memory controller and possibly internal bus/crossbar switches. From SemiAccurate’s dive into the current state of FPGAs over the past day, we were able to dig up technical information that strongly suggests Xilinx’s Virtex Ultrascale+ line has a built in hard AXI bus and switch plus hard memory controllers, but not necessarily hard HBM controllers. Other souterces think that the Altera/Intel Stratix 10 does not have the hard internal AXI crossbar or HBM controllers.
From here things are getting a little hazy, we found that Xilinx is shipping at least three full families of their 16nm FPGAs, one of which is the Virtex Ultrascale+ which some variants of sport HBM memory. If you look at the PDF here you can see the variants with HBM, which as far as we can tell are not shipping, and see the AXI bussed called out directly on those variants. (Note: Parts VU31P, VU33P, VU35P, and VU37P) Our sources say some of the variants without HBM which are shipping now have hard memory controllers but whether they support HBM directly is not known. From the looks of things the change of a memory controller would be a minor variant of the Virtex Ultrascale+ line from the already shipping parts if it is not already there but dark. If Xilinx gets back to us with an official comment about the controllers, we will update this or put out a new article on the topic.
Intel on the other hand is in a bit more of a bind. Their Stratix 10 MX is a curious beast, and by that we don’t mean they would have to use a fair chunk of gates to interface with HBM which could limit real world usable memory bandwidth. That is a problem but not THE problem. The problem is that the Stratix 10 MX with HBM is the same die as the shipping 2800s that don’t support HBM. If so how are they interfacing the HBM with the 2800? Do they use lots of gates again? Here is where things get a bit weird.
Packages Full Of <Censored>:
The answer is simple. Actually not, it is extremely complex with all the cost and yield implications that phrasing means to semiconductors. SemiAccurate moles say that the Stratix 10 does not have SerDes capable of interfacing with HBM at all. When we asked about why there was this glaring oversight some sources had no clue, others pointed to the historical nature of Intel/Altera’s SerDes. Altera traditionally used analog SerDes while Xilinx has preferred more digital SerDes.
That hint dangled in front of us we started talking to process folk at a big unnamed semiconductor company in Santa Clara. They confirmed that Intel’s 14nm process does not seem to play nice with analog bits, something SemiAccurate has heard for years now. This would explain the lack of high end SerDes on the highest end Intel/Altera FPGA die itself. But if this is the case, how is the Stratix 10 constructed? Again back to the weird stuff.
As Intel mentioned in their release, the Stratix 10 MX uses Intel’s EMIB to connect the FPGA to the HBM memory. Specifically they said, “These DRAM layers sit on a base layer that connects to the FPGA using high density micro bumps.” This is basic HBM construction, memory layers with a logic layer on the bottom, it is an industry standard. (Note: Our article is here and yes we know the pictures are missing, we are working on fixing that.) Then they say,”The Intel Stratix 10 MX FPGA family utilizes Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) that speeds communication between FPGA fabric and the DRAM.” Only one problem, this statement is not true.
SemiAccurate is aware we are calling Intel liars here but our technical information leaves us without any doubt on the matter, Intel is fibbing. Why? The SerDes in the Stratix 10 MX does not appear to be able to support HBM so Intel has made a workaround. To make HBM work they had to spin a chip with an EMIB interface on one side and HBM pinouts on the other. This sits between the HBM and EMIB and is something Intel conveniently forgot to mention in their release.
There Is A Good Reason:
Why? Because it points out how badly broken the Intel process is for analog and for foundry customers, not that there are any left. The two might be related. Moving back to FPGAs, the first problem for Intel is the process that this interface chip is made on, 20nm, not the cutting edge 14nm Intel is touting in their press releases. Worse yet it is made on TSMC’s 20nm process because their analog IP works. Some sources indicate this may be the SerDes block from the Arria 10 built on the same process with an EMIB interface grafted on. In any case it would be extremely embarrassing for Intel if news that their 14nm process is pretty much broken for analog designs and they had to turn to a -2 TSMC process to bail them out. Can you imagine how stupid they would look if word got out, so don’t tell anyone. It also sheds a lot of light on why Sophia was delayed, delayed, delayed, then canceled with no explanation, doesn’t it?
In any case it is pretty clear that Intel is not hooking an HBM stack to their FPGA because they can’t, it doesn’t work. It is also pretty clear that they had to fake parts because it appears they don’t actually have them. At this point you might be questioning how we can claim this in light of us saying that Intel/Altera was indeed shipping Stratix 10’s to customers now. This is why we parsed the words so finely earlier and picked on the choices they made.
SemiAccurate’s sources are saying Intel is shipping Stratix 10 2800 parts now. They are also shipping Stratix 10 2800 parts now with EMIBs and the TSMC 20nm interface pads. What we can not find is someone with a Stratix 10 2800 with EMIBs, TSMC 20nm interface pads, and HBM memory. This is not a minor point but if you do a lot of yoga, come from a family of circus contortionists, and parse every word of the Intel release and quotes to SemiAccurate just so, you could get most of it to pass legal muster. Barely. But not all of it.
Conclusion But Not The End Of The Story:
So where does that leave us? Intel made claims about being first that appear to be flat out false. They showed a ‘picture’ of their new product that was obviously a photoshopped fake but sadly not the worst job of it they have done recently. As usual they offered no technical explanations because as we showed, reality would be both embarrassing and raise a lot of questions from analysts should they read this far without permanently induced narcolepsy.
The painfully stretched answers to SemiAccurate’s questions shows how far the company is willing to go to split hairs in the hopes of hiding their problems. While it took far more research and time than we expected, SemiAccurate is glad to say that if you made it this far in the tale, you now know much more of the truth.S|A
Latest posts by Charlie Demerjian (see all)
- Intel shows off 10nm 112Gbps SerDes - Mar 12, 2019
- Intel releases Compute Express Link spec - Mar 11, 2019
- Qualcomm rolls out a second gen 5G modem called X55 - Feb 19, 2019
- What is Intel’s Foveros tech and what isn’t it? - Feb 11, 2019
- Why SemiAccurate called 10nm wrong - Jan 25, 2019