AFTER THE KEYNOTES of the three Common Platform partners, Samsung, Global Foundries, and IBM, three customers took turns at the podium. The first one up was ARM, and the talk centered around familiar themes, power and integration.
Most of keynote, given by ARM’s CTO, Mike Muller, was on power and scaling, a familiar theme to anyone watching semiconductors evolve over the last decade. The idea is simple enough, computers are getting smaller and smaller, and using more power per unit area than ever before. Things are getting to the point of being critical, and power use, or cooling, depending on how you look at the problem, is the main limiting factor for modern chips.
If you think about it, a computer has gone from the size of a large building just post-WWII to a small box that fits easily under your desk. If you continue the trend to laptops, MIDs and phones, the volume of the devices has gone down by many orders of magnitude. Having misspent my childhood in one of these retired post-WWII computer buildings, going from 50K+ square feet with 30 foot ceilings to a pocketable toy is quite the shrink. Until fairly recently, the power needed also shrunk commensurately, and the performance went up too. This is classic Moore’s law, the transistor count will double every 18 months, something most people looked to as saying performance will double in the same time. Again, until fairly recently, that was the case.
The problem is that once you have a desktop PC chip that uses tens of Watts, if you double the transistor count you also double the power use. For a chip line to not melt a hole in the earth after a few shrinks, you need to halve the power used per transistor every shrink too. Until fairly recently, that was the case, and the semiconductor industry was famous for delivering huge performance increases year after year in a smaller package that used roughly the same power.
Over the last decade, that power use has crept up, and the rate of increase is increasing too. Not a good sign. Mr Muller pointed this out with a nice chart that showed that scaling is still working for physical size and current, but not as well for capacitance, and voltage has effectively stopped dropping. What this means is the power consumed per circuit used to go down by a factor of 1/(a^2), where ‘a’ is the shrink factor, it now decreases by 1/a.
For those that don’t do graphs and intersection points well in their head, that means the power is going down linearly now when it used to be an exponential drop. If you are power limited and just about every chip out there is, your transistor growth is also linear now too, not exponential. This means that, for the most part, chip performance is now on a linear curve as well. Pity the GPU makers…..
Mr Muller summed this up by saying the first wave of computing, defined by mainframes and minis up to the 1980s, was defined by adding performance with each new model. The 1990s saw the advent of the PC, and the overriding metric for that era was performance/$. In the 2000s, notebooks were the hot commodity, and those added another metric, power use. The dominant factor here was performance/(power * $), basically that if you wanted to sell a chip in to that market, power use was a very real concern. Power use could go up, but performance had to go up commensurately or more.
The future as he sees it will be dominated by ‘mobiles’, be they phones, MIDs or whatever form factor dominates. These have very different requirements from a laptop, all-day battery life, days of standby, always on, and many other things that a PC was never engineered to do. The overriding concern for this era adds another metric to the metric, energy cost.
With laptops, the problem was more one of finding an engineering solution to a problem of power draw. In the future, the question will not be, “Can we do that?”, it will be “Is it worth it to do that?”. Cost of energy is increasing so the problem becomes one of how to get a specific performance level with the minimum Watts used. Performance going up does not matter much any more, the unwritten message is that we are on the verge of ‘fast enough’.
Strangely enough, ARM is very well positioned here, they have been designing chips that use power at levels that round to zero for years. Every other CPU company out there is doing the same to one degree or other, and the peripheral chip makers are also following suit. In very short order, every chip out there is going to have as standard what would be considered bleeding edge power management features a few years ago.
Semiconductor foundries are going to play their part in keeping scaling going as much as possible while using as little power as possible, but the days of easy and assured power scaling is over. New materials and tweaks on the atomic level will help, but will not get us back to where we were.
On that down note, things turned to the more technical side, and the role ARM was playing there. On the 32nm process, there have been ARM cores fabricated on it as early as 2008. IBM made a chip called Explorer in July of that year, followed by a full Coretex-M3 in October of that year, and Global Foundries did the same in May of 2009.
This was followed up by Alpha PDK (Product Development Kit) IP validation chips from IBM in June 2009 and Samsung a month later. Most interesting is that the chips listed as being on the 32LP TC1a process from IBM and 32LP TC1b process from Samsung. Full silicon validation of the ARM IP was first done by Samsung in February 2010 on a process labeled 32LP TC2.
That said, 32nm is almost old news by now, and 28nm is far enough along so there won’t be any major changes. 20nm is the next big thing, and ARM did not disappoint there. The company talked about their CP (Common Platform) 20nm SOC test chip based on a Coretex-M0. This core is .2mm x .2mm and contains 8K gates, 20K if you count the entire processor subsystem. This was overlaid to scale on an ARM2 chip, built on a 2µ process with 6K gates in total. The Coretex-M0 was a speck on the older chip, and probably used a commensurate amount of power.
Now that a company can make a CPU that is 1/25 of a square mm but has more performance than a cutting edge RISC machine from a few decades ago, what do you do with them? NXP is currently selling their Coretex-M0 variant for $.65 each, how much cheaper do you need? How do you communicate with them, or do you at all?
There isn’t a specific answer to these questions, but the goal is what many call the ‘internet of things’, basically everything will be sensor enabled and aware of what it needs to be aware of. If you can make a chip that small and power it, all sorts of opportunities become available.
This is where advanced packaging comes in, something that most people ignore, but it is the most important technology trend for the near future. Packaging doesn’t necessarily involve stacking CPUs on CPUs or memory on memory, it can be much more, and not just constrained to compute devices.
Muller showed off one project that they have been working on, a glaucoma sensor. That is an easy problem, they have been around for years, and work OK. When you go in to the doctors, they measure the pressure in your eye, and it can change quite a bit depending on how you are feeling, time of day, and some environmental conditions. What you really want is something that measures the pressure in your eye every few minutes or hours, and reports that.
The problem is that it takes a trained professional to take those measurements, not to mention a somewhat intrusive set of devices. You don’t want to spend a month at the doctor’s office getting poked in the eye every few hours. If you can’t see where this is going, pun intended, the idea is to put the sensor in your eyeball itself.
Here is where the problems begin, how large of a device can you put in someone’s eyeball? How do you power it? How do you read the data from it? Those are the big questions, but far from the only ones, and those are the kinds of challenges ARM is looking at.
The answer to the first question appears to be a few cubic mm for the size limit, Bigger than that is said to be a no-go for most eye doctors, so there is your size constraint. How you power it is likely the more important question, and that is fairly well solved by solar cells and batteries. Any battery that will fit in a fraction of 1mm^3 is not going to power anything for long, so a combination of a solar cell and battery are needed to tide the device over during periods of sleep and darkness.
Talking to the device is a little more complex, it needs two things for that, a timer and a radio. The radio is obvious, it needs to talk to an external reader, most people would object to having their eye cut open weekly to read the data.
The timer is a critical part of the communication and power systems. Having a radio on all the time is clearly impossible given the power constraints, as is waking it up at regular enough intervals to read it during an office visit. The solution is to have the device wake up only at very certain times, and the carrier makes sure there is a doctor there with a reader when it does wake up. This makes the whole thing doable with the absurdly tight power budget imposed by the size and location of the sensor.
ARM based glaucoma sensor stack
Above you see just that, a 1 cubic mm embeddable eye pressure sensor. On top you have two solar cells made on a standard .18 micron CMOS process. Those are wired to an ARM Coretex-M3 running at it’s lowest voltage threshold with a pressure sensor and radio on the die. Below that you have a 12µAh battery to tide it over through nights, blinks, and movies. The entire package is said to be 8.75mm^3.
Things like this sensor and many others are what Mr Muller sees as the future, and they will likely talk to phones, not PCs for the most part. Performance will be dictated by how much computer power you need to get the job done, and how little energy you can consume while doing it. Margins will be reduced, and the more efficient a company is, the better they will do. It is hard to argue with any of that.S|A
Latest posts by Charlie Demerjian (see all)
- HyperX ships it’s 60 millionth enthusiast memory module - Oct 15, 2018
- Bittware/Nallatech water cools 300W of Xilinx FPGA - Oct 12, 2018
- More on Intel’s 10nm process problems - Sep 17, 2018
- Intel puts out another 14nm 2020 server platform - Sep 11, 2018
- Why Can’t Intel Supply Enough 14nm Xeons? - Sep 10, 2018