It looks like the MRAM gates are wide open with Spin Transfer Technologies revealing their wares. More interesting than the official news on when they are releasing products are what they are releasing and how.
SemiAccurate has been covering MRAMs for a while now, specifically Everspin’s products. When that company announced they would be working with Globalfoundries on MRAM as an IP offering for the 22nm SOI process and below, it looks like the news floodgates were opened. Today Spin Transfer Technologies (STT) is opening up about their products and plans and there are some interesting technical bits among the bit cells.
Lets start out with the official news, STT is going to be working with an unnamed foundry partner, possibly more than one, on using their MRAMs as embedded flash replacement at 28nm and below. It will be available as IP and discrete chips to suit your use case, pick your placement. The IP variant is promised to integrate with analog, high voltage, and other processes too.
There are three official news points today starting with STT delivering 100% working ST-MRAM samples to customers in Q1/2017. This will be followed by embedded production parts in 2018 as well as STT’s own commercial chip offerings that year too. If you noticed the 100% working bit in the samples, remember that, it is a key point when dealing with ST-MRAMS.
The reason for this is that ST-MRAMs are probabilistic devices in nature, specifically the pMTJ is in how it writes. This isn’t to say there is an error, just with physics at this level the write is statistical in nature. This can lead to a lot of headaches for developers, especially when you have that once in a few million writes error or more accurately nothing happening. If you look at how the pMTJ itself works, it helps a lot in understanding why things go or don’t go bump in the night.
The idea behind a pMTJ
There are three parts to the pMTJ, a reference layer, a tunnel barrier, and a free layer. The reference layer is both a magnetic reference and a magnetic polarization device which you can use to program the free layer. If you set the electron spin of the free layer to be magnetized in the same direction as the reference, the entire device has a low electrical resistance. Opposite directions add up to high resistance, zero and one. As you would expect from anything dealing with setting electron spin, quantum effects come into play and things happen a bit oddly compared to the world we live in, hence the probabilistic nature of the write process.
Add a second polarizer for programming
This is where STT adds their secret sauce to the everyday world of making pMTJ ST-MRAMs. Yes that was sarcasm, even the vanilla versions aren’t close to easy and nuance does matter a lot. In this case they add a spin polarizer to the top of the device and some proprietary circuitry for reading and writing as well. How it works we can’t say for now but it is how STT is able to achieve the 100% working cells. Unlike basic semiconductors, 100% yields in may not always lead to 100% cells that meet a performance spec so the bulk of what STT does is close that gap through proprietary magic.
Blame Microsoft anti-competitive games for the formatting here
The most interesting part about is the above slide where WER is Write Error Rate and endurance is just that. WER drops with write times so the longer you apply the write voltage, the higher probability of the write working. Luckily there is a high probability that this makes sense to you, it is similar in concept to how many other memories work, flash being the key one. What the graph is saying is that if you can drop the WER low enough, at a certain write window the error rate will be below the endurance of the memory so on average a cell will die before it sees a probabilistic error.
That brings us to the next point, why not jack the write window way up and call it done? Write speed can also be equated to power used by the memory, the lower the better. ST-MRAMs are great for energy use because they don’t need refreshes but every electron still counts. The write window also determines the speed of the device and as always faster is usually seen as better. Currently the game is to make the devices faster, lower energy, more reliable, and with higher endurance. Any one of these specs is easy enough to optimize for, all at the same time is really hard.
As with most other memories, STT is optimizing for four key areas, eNOR, eSRAM, IoT, and XIP (eXecute In Place) by picking the dimensions(s) they optimize the device for. These are in addition to the normal DRAM replacement use case, we consider that one a given. Those samples promised for Q1/2017 are aiming for two different vectors, reliability and manufacturability and they will be combined for the 2018 product. STT says the 100% working part is done and they are ramping volume for samples.
Which brings us to the next point, how STT is making samples. We won’t go into the details about how long it takes to get test silicon back from a foundry on a current node but it is many weeks best case. Throw in another few layers on a specialized magnetic line and you are talking months to get your test back, something that hampers the iterative nature of the development process.
Nice tight clusters and sizes are good
STT saw this coming and built their own Class 100 magnetic back-end operation in Fremont. They claim a <10 day cycle time with capabilities for feature sizes down to ~20nm with features matched to their requirements. In the first 34 weeks since it went online December 28, 2015, they claim to have processed ~40 lots or more than one iteration a week. Compare this to the normal process of 1-2 a quarter and you see how progress is made. The only negative thing we can say is to make a joke about Fremont but that would be too easy.
So in the end STT is finally outing what they are doing with a roadmap to customer MRAMs. In Q1/2017 they will deliver 100% working ST-MRAM samples and in 2018 we should expect to see embedded and discrete devices using their tech. This is made possible by adding a second spin polarizer to the top of the device and iterating fast in their on magnetic back-end fab on premises. It will be interesting to see how it all turns out when devices are finally announced, stay tuned.S|A
Latest posts by Charlie Demerjian (see all)
- AMD’s 3D V-Cache takes the advanced packaging lead - Jun 1, 2021
- AMD releases CPUs and GPUs at Computex - May 31, 2021
- Intel’s honesty shows through at Computex 2021 - May 30, 2021
- Qualcomm launches the Snapdragon 7c2 compute platform - May 24, 2021
- Qualcomm announces modem goodies at their 5G Summit - May 19, 2021