AMD just launched their 256 core Venice CPU with some subtle and not so subtle changes to the architecture. SemiAccurate will walk you through the details of this new monster from overview to details.
Family History:
If you are reading this article, you are probably familiar with AMD’s server architecture, the same basic concept has held since Rome in 2018. Take a central hub called the I/O Die (IOD) and hang a bunch of Core Complex Dies (CCD) off of it. Think hub and spokes. Over the years those CCDs have grown from 8c to today’s 32c beasts, and the IODs have hung various numbers of CCDs off of them. Those IODs have also increased in capabilities and in the biggest change, there are two of them per socket this time around, six if you count all of the new variants. With that in mind, from a big picture overview, things don’t look all that different.
A Tour of Italy
Variants Abound:
Lets start out with a little nomenclature to ease the rest of the article. There are three, four sort of, versions of Venice. There is the big SP7 version, a dual socket beast with 16 DDR5-8000 or MRDIMMs at 12.8GT/s channels in a 76x80mm package that supports 2S systems. Below that there is the SP8 platform with 62.5x80mm packaging but only a half the memory channels. Then there is Verano which is the Venice CCDs coupled to IODs that support LPDDR5x-8533 on SOCAMM modules. Lastly there is Venice-X on SP7 which is a standard Venice with stacked cache on each CCD. From a high level they look very similar to their elders dating back to Rome, but this time around it is the biggest architectural change in the platform since Naples. Lets look at each in detail.
The standard Zen 6 offering is Venice on SP7, a dual socket system with up to 256 cores and 512 threads per socket. Each socket supports 16 DIMMs of DDR5-8000 but only 1 DIMM per channel. If you have seen an SP7 system with side by side sockets and the full 32 DIMMs, you understand how tight the packaging needs to be to fit in a standard rack. It makes things clear as to why AMD doesn’t officially support 2DPC on SP7. This borderline ludicrous number of channels plus the CCD links explain why the IOD was split into two.
The 256c Venice CPU
AMD Venice overview
Above is a 256 core SP7 Venice. You can clearly see the two central IODs and the eight 32c CCDs below that. The four little bits on top are power circuitry, IPDs if you are into that kind of thing. If you look below you can see the 96 core Venice-F on SP7 and it looks really different. You may notice the non-symmetrical nature of the layout, it uses eight 12c CCDs that are much smaller than the 32c variants. The cores are not the same between them, the 12c CCDs are for the high speed -F variants that change more than clock and count. Lastly you will see that there are mechanical supports between the CCDs to make up for the smaller size. We will cover the cores later in this article, don’t worry about that.
The 96c Venice -F
Venice SP8 Overview
SP8 as shown in the diagram above is similar to SP7 but uses a smaller package and only supports eight DDR5 channels. To make up for that lack of bandwidth, it allows for two DIMMs per channel. AMD did not say how much speed you lose by adding that second DIMM but in the past, lets just say it was a sub-optimal configuration for latency. Then again since the largest SP8 CPU has 128c so it isn’t a massive loss. Even the 96c ‘big’ core variant should do OK in this configuration. For those of you that didn’t just do the math in your head, SP8 IODs can support 8x 12c -F CCDs like SP7 but only 4x 32c ‘small core’ CCDs.
Venice Chiplet Architecture
Lastly we come to Verano, the LPDDR5x variant of Venice, it has a unique IOD not just because it has a completely different memory controller. LPDDR5x wiring means AMD needed to put two memory ‘wings’ called MCDs on each side of the IODs, think of them as very expensive breakout boxes. Since Verano was only half launched at the Venice event, they didn’t show chips, systems, or even specify the memory other than to say there are 24 channels at 8533MT/s. Instead of DIMMs Verano systems use SOCAMM modules and the systems only go up to six populated CCDs of either size with two mechanical blanks.
The Four Horsemen
IODs Aplenty:
That is the overview, lets look a bit deeper into the IODs and CCDs now, we will leave Verano mostly out because AMD didn’t talk details on it yet. Remember when we said the IOD was split into two? You can see it above and they are rotated 180 degrees to each other so the DDR5 ports can face out while the D2D interfaces are up against each other. This is an obvious thing to do and it explains why the 96C -F parts are arranged non-symmetrically.
Also note that each 32C CCD has 4x D2D connections to the IOD for the 32c CCDs but only 3x for the 12c CCD. This isn’t conspiracy, the 12c CCD has far less compute throughput, 12×5.3GHz is a tad less than 32×4.1GHz. That tad is about half or far less than 75% available bandwidth so the smaller CCDs have much more bandwidth per core. Losing that link saves die area and power without costing any performance so it is a win/win.
If you look at the layout of the last four generations of Epyc SoCs, you might notice that the CCDs are rather distant from the IODs, mainly for thermal reasons. This meant the use of SERDES to shuttle the data between the dies over a long distances on organic packaging. It worked fine but burnt a fair bit of power, especially in the early generations. Venice puts the CCDs right up against the IODs even though there is ample room on the package to spread things out. Why? Power and die size.
Instead of SERDES pushing the bits across a rather lossy organic package, Venice uses EFB or Elevated Fan-Out Bridges to connect the chiplets. Think Intel’s EMIB without Intel while dancing around patents and you get the idea. Embed a bridge in the substrate and have the two chiplets talk directly over silicon. This also avoids burning area for the SERDES on both sides of the link and saves tons of energy going over the silicon bridge. Lower power, higher cost, complex construction, more tricky thermals, and closer but smaller dies. This isn’t to criticize what AMD did, they appear to have done the right thing for the right reasons here, it saves power and die area which will pay big dividends on the TCO side. Additionally a few dollars more spent on packaging isn’t going to break the bank of a multi-thousand dollar server CPU.
Remember when we said that the number of DDR5 channels explains why the IOD was split in two? The pins for high speed memory really need to be placed on the edge of the die for a number of reasons we won’t get in to now, and they compete with the high speed CCD links for that space. Sixteen channels and 8x 32C CCDs would require more edge/beachfront area than a single rectangular die could support. If you skew the X/Y ratio enough to support all the needed pins, it wouldn’t fit in the reticle, or at least would waste a large amount of wafer space at the edges or leave white space in the center of the die. The answer was to split it up into two rectangular dies and put the DRAM pins on the shorter edges, D2D high speed links on the long ones. Simple but it requires two dies. While AMD hasn’t announced any Threadrippers for this generation, it is probably a good bet that we will see a single IOD CPU hit the market sooner or later.
SKU Stupidity:
So that’s the overview, lets look at details starting with the SKUs offered which is a bit of a problematic issue. On the event pre-brief, AMD listed 32 SKUs across SP7 and SP8. 19 were general parts, 8 -F High frequency, and 5 were 1P SKUs. The table had cores, model, default power, Fbase, Fmax, L3, CCD Type, and price. During the real brief that table was excluded so we asked for the list. We got this link with a laughable subset of the data, 10 products in total with price and more excluded. So we should just scrape the pre-brief video and use that, right? Well they asked us not to use anything from that deck, and in fact they didn’t provide the deck even though they said they would. We abide by our agreements and so we can’t publish the list. Enjoy the joke on the web site, own goal guys.
So with that out of the way the official list says cores range from 64-256, -F being the High Frequency ‘big’ cores, G in the second digit is a SKU for Helios or Helion only, we don’t actually know which one, and no questions were answered. Also not called out are the socket type, it is just stupid but we agreed so… Similarly power is listed from 220W-600W on the public chart, there are more numbers out of that range in the non-public ones, many more.
PCIe 6 In Quantity:
Venice 1P vs 2P layouts
This is where things get interesting. SP7 supports two or three links between sockets, if you choose two you can use those idle links for 2x additional PCIe6 slots. Three links obviously gives you more bandwidth between cores so depending on your workload, more slots may not be the better way to go. SP8 only supports two links between sockets. The links are Gen 5 Infinity Fabric which runs at 64Gbps, coincidentally the same speed as PCIe6. What are the chances of that, almost like AMD did the smart thing and re-used PCIe’s physical layer for IF. Oh wait, they did the smart thing again. The result is 128 lanes of PCIe6 in 2P SP8 configurations, 96 in SP7, plus a few PCIe4 lanes for housekeeping if you want to wire them. CXL3.1 is also standard but we can’t say how many lanes support it, some slides suggest all lanes but don’t take our word for it.
SP7 and SP8 have different IODs
SP8 is a new pair of IODs, new for added and subtracted features, pair for the same reasons as SP7, beachfront area. Other than that not much more to see here, half the memory channels, many more PCIe6 lanes, especially in 2S configurations, and 2DPC support. The speed drop at 2DPC is not on the slide above, again we asked and got no reply.
Verano is very different
The last platform is Verano and it is really different, starting with the name SB1. Verano can use either 12c or 32c CCDs but only six of them per system. Memory is done via the wings we told you about, each supports 6-channel LPDDR5x at up to 8533MT/s for a total of 24 channels on removable SOCAMM2 modules. Probably the most interesting bit is that since DDR and LPDDR communicate in very different ways, it has some cascading effects on the system itself.
The most obvious change is the IOD with a completely different set of memory controllers, plus the breakout ‘wings’ for the required wiring. Those protocol changes go as far as changing the IOD to CCD communications. AMD lists, “Enhanced probe-response data (32B) and write-heavy traffic (25B) performance”, then, “Increased ports, more BW/CCX, increased sharing”. We can’t say if this necessitates changes to the CCDs themselves but we doubt it. As for the details, you have what we have, hope it is enough.
Overview Over:
So with that rather scattershot overview of Venice, Venice -F, Venice-X, Verano, Sockets SP7, SP8, and SB1, we have the groundwork for the next level down, the cores. Then we will look at the new features of Venice et al, both at the core and the platform level. Unfortunately that will have to wait until the next part of this article, stay tuned.S|A
Charlie Demerjian
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