Manufacturing History (Revised):
If you recall last year, Intel had a “manufacturing day” to tell you all about the glories of their manufacturing process. The official story, now shown to be the lie we told you it was, was that 10nm wasn’t actually late and Intel didn’t fall off the Moore’s law train. Instead they intentionally took a new tact called Hyperscaling which was said to slow down the cadence of shrinks but increase the magnitude of each step. Most of the financial world bought it, the few that didn’t had their microphones taken when they tried to ask pertinent questions. (Note: This is not a joke, the details are in the link above)
If you were cynical or more to the point knew what was actually happening behind the scenes, you would be horrified at the technically legal but still misleading statements given about the state of process technology at Intel. SemiAccurate was the lone voice detailing the problems from the very start, to the delays, and to the final non-admission that things were never going to work. Hyperscaling is BS and was directly contradicted by the very words of the presenters.
Servers – The New Spin Battleground:
Why is this relevant? Mainly because 10nm is now 4 years delayed (Note: That means a 6-year shrink cadence, not a 4-year one) so badly that multiple generations of Intel server products are delayed too. Intel’s Purley, aka Shylake-EP/SP was a solid chip betrayed by a 3x price increase. OEMs are reporting that sales are awful, mainly due to the fact that the volume SKUs are TCO underwater compared to their Broadwell-EP predecessors. What did Intel do to fix this product mess? Forced customers into Purley. If you don’t think this will have long term effects… well they are already visible if you know where to look.
Then we come to Cascade Lake, the successor to Purley. It brings quite literally nothing to the table, it is a minor bug fix to Purley and nothing more. OK with the Meltdown and Spectre patches it will slow down a bit, but there is nothing really new in Cascade Lake. TDP goes up from ~160W for mainstream Purleys to ~200W in mainstream Cascades which is how they get the very modest performance increases.
Couple this to some, but not all, of the features promised for Purley and you have Cascade Lake. No more cores, no more memory channels, no more PCIe lanes, and nothing to close the yawning gap to AMD’s Epyc. Performance does go up though, but less than the TDP increase as a percentage. How much? 6-8% on a per-socket basis meaning Cascade will still be TCO underwater compared to 2015’s Broadwell-EP.
Luckily Intel has a cunning plan there too, raise prices from Purley’s ~$13,000 to ~$20,000. No that isn’t a joke, a 6-8% performance boost almost completely due to TDP raises comes with an ~$7000 price increase. Did we mention AMD’s Epyc, which is about 15% slower on a per-socket basis, costs less than 1/4th as much? And has more PCIe lanes, more memory channels, more cores, but does take more energy. Over the service lifetime, SemiAccurate feels safe in claiming that an Epyc box won’t consume very much of the $15,000+ delta, per CPU mind you, in electricity even at the high rates in some countries.
Cascade is not due out until Q4/2018 for the hyperscalers and Q1 for the rest of the world, a ploy that shattered Intel partners’ trust the last time the company played this game. According to the latest leaked Intel roadmap, volume for Cascade won’t start it’s ramp until ~1Q before AMD’s monster Rome CPU. (Note: The leading edge of the boxes are for PRQ, not for volume release so add at least 1Q to the times)
It won’t’ be a fair fight. Why? Rome will beat Cascade by more than 50% in per-socket performance, likely tie or win on a single threaded basis, and more than double the Cascade’s core count. Please note that by more than 50% we don’t mean a little more, we mean a lot more, think abusive rather than hair’s width margins.
There are Cooper Lake SKUs that can close the gap a bit, the 3-die water cooled 350W Cooper-AP that requires new infrastructure will roughly halve the performance gap at a much higher price and significantly higher TCO. How bad is Cooper Lake? Normalized to Purley it is a bit less than 40% faster. This may seem like enough to hold the line but Cooper is not set to come out until about a year AFTER Rome, still have six memory channels, less PCIe lanes, and all the rest. And that is for the monster 3-die new socket version, the mainstream Cooper Lake won’t even reach those uncompetitive heights. Intel putting Cooper Lake out is nothing more than a desperation play.
Update = Aug 7, 2018 at 1:25pm: Changed “lower TCO” above to the intended “higher TCO”. Nice catch NTMBK.
Update 2 – Aug 7, 2018 at 2:20pm: Changed 2019 to 2020 below. Again sorry about that.
Ice-ing On The Spin:
Cooper Lake is due out in early 2020, at the moment, and is going to be followed by Ice Lake which SemiAccurate exclusively told you was a mid-2020 product. Guess what? Ice Lake is slower than AMD’s Rome. Significantly slower. That is OK though because AMD will have Milan out at the same time as Ice Lake and Milan raises the bar by solid double digit percentages once again. Ice? Intel is claiming that it will raise the bar by less than 20%, but that is before the process changes from the old 10nm to the new 10/12nm take a hit out of the gains. SemiAccurate hasn’t seen the new numbers in enough detail to say much other than performance will go down from the current goals.
Gasping For Air:
Worse yet for Ice Lake the big Achilles Heel for their architecture, inadequate QPI bandwidth, won’t be addressed. Sure it goes up from 10.4Gbps to 11.2Gbps, but given the core count and memory speed increases, it is woefully inadequate. Sapphire Rapids brings things up a bit but won’t reach levels where AMD’s Rome will be three years earlier. AMD isn’t going to sit still mind you, but the current Naples/Epyc is already faster than Sapphire will be in that regard.
This means that even if Intel has a single core advantage, their other main strength, scaling, flips to a liability. It is bad enough that several OEM sources surveyed recently are concerned enough to scale back the lucrative multi-socket designs and look to AMD for a solution. This may seem like technical minutia but it is what an ~5 year platform delay brings to the table.
Onward And (Not) Upward:
So Cascade Lake doesn’t hit a 10% performance gain for a $7000 price increase, and AMD’s Rome beats it by more than 50% in performance. Cooper Lake which comes out several quarters after Rome roughly halves the gap. Ice Lake again closes the gap to Rome a bit more, but does not come close to beating it. Once again Ice Lake is released significantly after Rome, and that assumes Intel’s 10/12nm process is as on track as they claim.
Unfortunately for Intel, AMD’s Milan come out a bit before Ice and, well, beats it like a drum. We have been asked not to reveal specific numbers yet but the ones SemiAccurate received from a trusted source show Milan widening the gap to Ice by at least mid-double digit percentages.
Once Rome comes out in Q2 of 2019 or so, AMD never has a performance lead of less than 25% per socket, and that is the worst case for AMD vs the best case for Intel, fudged a lot in Intel’s favor on top of that. After Rome, the server fight isn’t even close, AMD walks away laughing. And costs a fraction of what Intel does. And takes less energy to run. And has better scalability. And has more features. And is more flexible. And has a functional process to build it on. And has a process lead. And I could go on but you get the idea.
Luckily for Intel, they have a plan. That plan doesn’t involve silicon, it involves gathering the press and analysts and lovingly providing FUD before the proverbial excrement hits the rotational parts of the air movement device over the next few quarters. On the silicon side there is absolutely nothing Intel can do to combat AMD, their offerings are not even adequate much less competitive, and priced much higher. Intel knows this.
Why does SemiAccurate say that Intel knows? We have seen their internal documents that show exactly how frightened the company is. The documents go into specifics we don’t feel are appropriate to discuss publicly but there is one thing we can say, Intel knows their position. One of the documents says in no uncertain terms that the company understands they will not be competitive in the server market until AFTER Sapphire Rapids, the 2022 server part. AMD has a clear run in Intel’s core market for at least 4 years.
Intel has two choices after AMD launches Rome, three if you consider now illegal market manipulations. We will discount those. Those choices are drop prices or cede marketshare. Intel can’t drop prices, their ~3x price increase from Broadwell-EP to Purley is the only reason their financials are so solid. The ~$7000 price gain from Purley to Cascade, coupled with a steep rise in the percentage of MSRP that Tier-1 customers pay, says Intel knows they can’t touch margins.
So they have to cede marketshare. How much? They know and it makes the 15-20% number that CEO Brian Krzanich was said to have mentioned look small. OEMs that SemiAccurate regularly talk to are already jockeying for capacity for AMD’s Rome and that is only the start of the game. You can figure out the magnitude of Intel’s share loss if you know where to look, it is a big number.
So what is Intel to do tomorrow? Spin until you get so dizzy you fall over, then flail. Numbers will be presented that show large potential increases in performance based on wider SIMD vector widths and other very specific benchmarks. The numbers quoted above are for real world benchmarks from key Intel partners, not press and analyst specific fantasies. If you doubt that, compare the launch slides for Intel’s latest 4-5 CPU revisions to the real world gains and you will see what we mean.
But the key message is a very cunning one, datacenter TAM. Intel has been talking up the TAM for the datacenter lately, purposefully conflating it with CPU sales. The datacenter TAM is going to skyrocket as more things move to the cloud and the PC/discrete server market is gutted. Look for the company to ‘unintentionally’ intermix datacenter TAMs with CPU sales in the hope that you don’ t ask questions about CPU share.
SemiAccurate has laid out a pretty stark picture of Intel’s performance and market competitiveness over the next 3-4 years. We are highly confident in the information presented because the majority of it comes from Intel’s internal outlook and documentation that was shown to us. They know they have no chance in their most lucrative core market, and are trapped between raising prices to keep margins up and cratering marketshare. Either way they lose because they aren’t close in performance once AMD’s Rome comes out.S|A
Bonus Code Name: Hill Ridge
Latest posts by Charlie Demerjian (see all)
- When will Intel deliver Ice Lake-SP in volume? - Jul 13, 2020
- How many cores does Intel’s Ice Lake-SP XCC have? - Jul 13, 2020
- Intel has another delay to a major server platform - Jul 9, 2020
- Qualcomm launches the Snapdragon 865+ SoC - Jul 8, 2020
- AMD updates Ryzen 3000 to Ryzen 3000XT - Jul 7, 2020