SiFive and FlexLogix have teamed up to offer embedded FPGAs in the DesignShare development program. This is the third IP vendor that SemiAccurate knows of to join that program and it is an interesting idea.
SiFive’s DesignShare program is unique in it’s aim to lower the barriers of entry for companies interested in making silicon. The SiFive IP is all open source so cost of the core isn’t the issue but the cost of the whole chip with ancillary IP could be. If you recall the SiFive business model is one that leverages a common open source theme, the basic IP is free but they can do the job you want better, faster, and cheaper than you can do it yourself. You could roll your on RISC-V SoC repeating the work SiFive has done, or for a small fee they can modify their work to your needs.
This model is great until you need other IP, which almost any non-vanilla SoC will, then it gets interesting. If you need an FPGA, crypto cores, or system monitoring/debugging capabilities, you need to negotiate all those IP agreements on your own. Then pay to incorporate them into the design. IP licenses like this tend not to be cheap, quick to negotiate, or very much fun in any way, think pain and lawyers.
DesignShare on it’s most basic level aims to cut this burden. SiFive has negotiated an agreement with FlexLogix for embedded FPGA cores so you don’t have to. When you buy the chips that result from your SiFive engagement, it is rolled into the cost, no lawyers, no pain, not time to market extensions, theoretically it is just a checkbox option on your RISC-V SoC. Same for Rambus and their crypto units and UltraSoC with their debug and control fabrics. More are said to come.
SiFive is aiming at small developers, think startups, that don’t have flocks of lawyers, much money to spend, and all the other things that a big company may have in place. With DesignShare they seem to have done the right things to lower the barriers to entry quite far, assuming you want to do a RISC-V SoC on 28nm or 180nm processes rather than say and ARM core on 40nm. SiFive’s claim of 100 chips for $100K seems quite doable and upends several business models in the process.
If you look at the costs for doing a traditional chip, 28nm masks alone can run several million dollars, and that is before IP licensing, development costs, masks, lawyer yachts, and the rest. This took silicon development out of the price range of most startups and all but an elite few academic projects. With SiFive the cost seems to be about 100K to get enough silicon to prove a point, be it a journal paper, PhD, or the next round of funding. The barriers are an order of magnitude less than the mask costs for a tapeout on 28nm alone.
So how does SiFive do it? On the IP side the core is open, the integration of the licensed IP is likely done once by the licensor and SiFive, and from there it is only modifications for each job. The IP is similarly negotiated up front with a small fee attached to each core similar to how it is done now. The biggest change here is that the IP vendor is not charging an up-front licensing fee.
Why? Because the usual costs that those fees cover, mainly hand-holding the licensee through development, is already done, or at least done only once with SiFive. The customer never talks to the IP vendor, something which likely relieves said vendor quite a bit. Instead the IP vendor only deals with a single entity who theoretically knows what they are doing and requires little if any hand-holding. Everyone’s costs go down.
That still doesn’t explain the mask costs and how they get around that little issue. SemiAccurate’s guess is that since SiFive is going to be doing this work for lots of startups, they can put several projects on the same mask set. The chips SiFive is making are not going to be very large, probably low tens of mm^2 on 28nm, so an ~600mm^2 reticle can fit 20-30 projects and produce about 100 of each chip per wafer run. This is normally untenable to even propose for normal development because companies don’t work well together especially in IP related matters. Since SiFive is the only ‘customer’ on the wafer, and the only one with access to the IP, they nicely sidestep the age old issue of sharing a mask set.
So what motivates IP vendors to hop on board this low cost open source train? Part of it is the cost associated with licensing IP as mentioned above is not there, but with 100 chips for $100K, there isn’t much money to be made even if the work they have to do is zero. This is where things get interesting, they IP vendors appear to be making a big bet, with fringe benefits. The bet is simple, they figure if 10 companies use their IP, most will fail. If one or two make a go of things, and a small percentage of those that survive go really big, there is a huge potential upside.
SiFive does most of the work so the initial effort expended to enable them seems to be money well spent to hopefully be in the next Fitbit, GoPro, or whatnot. The fringe benefit is that the IP vendor gets tens or more tapeouts and projects to verify their IP against. If the DesignShare process takes off, the vendor will likely get their IP ported to significantly more processes and foundries than they have the manpower to do themselves. “Our IP is tested in 67 projects on sale now” is a much better selling point than, “We really think it will work and not have bugs, honest”.
So that is what FlexLogix and SiFive are announcing today, that FlexLogix’s embedded FPGA IP is now in DesignShare. You can order up a RISC-V core on the Freedom Platform with and EFLX FPGA on 28nm and 180nm now, with the U500 platform coming later. This alone is not enough kickstart an ecosystem but prior DesignShare vendors Rambus and UltraSoC add a lot. With a few more on board SiFive may have a viable turnkey SoC to offer customers. If this model succeeds, the barriers to entry for new silicon designs will undoubtedly drop radically.S|A
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