AMD finally releases Milan/Epyc 7xx3

Not really late but welcome anyway

AMD EPYC LogoToday AMD finally launches Milan, the Epyc 7xx3 line, about six months after it went on sale. SemiAccurate can’t explain why this non-delay happened but now the server CPU is officially and publicly here.

AMD Milan Epyc 7xx3 SKUs and pricing

The raw data

There are now 15 Milan SKUs, more if you count 1S/2S separately, ranging from the 8-core 72F3 to the 64-core 7763. Clocks go up around 200MHz for peak turbo and down a bit for base, a good thing because it saves energy. TDPs are the same and Milan/7xx3 is socket compatible with Rome/7xx2, again a good thing as long as you are not horribly averse to updating a BIOS.

Couple this to the ~20% IPC increase for the Zen 3 core over the Zen 2 core,  something that translates to an ~25% perf/Watt increase, and you have a winner. That level of increase with no platform changes are fairly rare in the industry nowadays, and it is even more impressive given that the process, a TSMC 7nm variant, is pretty much unchanged since Rome. SemiAccurate released the full SKU stack a few days ago, along with some commentary so we won’t go over that again.

As you probably know, nothing is free and in this case Milan’s MSRP does go up a bit from $6950 for the top bin 7742 Rome to $7890 for the highest priced Milan, the 7763. Since price goes up by less than performance, ~13% vs 20+%, you probably won’t hear too many customers complaining. In any case MSRP is about as tied to the real world as a political promise so Tier-1 pricing may or may not bear any relationship to it. Since most Milans will be sold at volume prices rather than MSRP/box/tray, these numbers should be used as a rough guide only.

So what’s new? Not much on the silicon side, the CCDs have been out for months in Ryzen 5000 form and the IOD is almost a carryover from Rome. We say almost because there are some minor changes to the die for new features but nothing you would see in a die shot and the silicon area is unchanged. AMD has not built a Milan IOD with Rome CCDs but they said it should work in theory, the Milan changes are a superset of Rome’s so no problems are expected.

From a user perspective, the biggest visible change fixes one of Rome’s biggest glass jaws, 6-channel memory support. On the Epyc 7xx2 line, you could run a system with 2, 4, 6, or 8 DIMM slots filled but if you were not on 4 or 8, performance tanked. Why would any sane customer run with 6-channel memory over 8-channel? Think cloud providers trying to line up offerings with Intel’s Sky/Cascade line. If you did dare 6-channel, memory would not interleave and, well, just don’t. Milan fixes this so any memory channel count is interleaved properly. If you are a hyperscaler, you can drop Milan’s performance to that of Cascade now, yay?

The next big bang is on the security side with the inclusion of SEV-SNP or Secure Nested Paging. SemiAccurate told you about AMD’s security offerings on Naples and the second generation in Rome added a lot of features. This third generation adds a few more bits but nothing that will change the game. SNP basically keeps a malicious hypervisor from writing to guest pages. If you are wondering why this is necessary since SME and SEV can encrypt those pages so the hypervisor can’t see anything useful, it can still write to those pages corrupting data and crashing processes. SNP locks that attack vector out preventing a DOS attack.

One other new change is that secured guests can turn on debug registers which are correctly swapped out in hardware on hypervisor state changes to prevent data leaks. This could be done in software but it would take a lot more time and potentially have issues if not done perfectly. Now it is hardware controlled so again in theory it should be secure.

Memory protection keys are now user accessible so they can be turned on or off as needed without higher level intervention should you have the need. AMD is also implementing a CET Shadow Stack to prevent against ROP (Return Oriented Programming) attacks that are becoming a bit more common. All of these things require OS intervention so your mileage may vary. None of these security changes are world changing but they all help a bit.

On the instruction side there are two new AVX instructions and an inter-core interrupt broadcast instruction. VAES and VPCLMULQDQ are the AES additions and INVLPGB broadcasts interrupts. INVLPGB is the important one because of the recent core count explosion. Figuring out which cores to push a page invalidate to and then pushing it out possibly tens of times is slow and wastes bandwidth. INVLPGB broadcasts one packet to all cores which individually act on them, or not as the case may be. Each packet can have up to eight addresses to invalidate and they can be chained. When you are done, you follow it up with a TLB sync instruction and all is well. If you did it the old way, all would be well too, it would just take longer and suck more fabric bandwidth.

AMD Milan Epyc 7xx3 performance stack


So how does Milan perform? Pretty well, especially if you look at the new 28-core and 56-core offerings that some have suggested were only made to troll Intel. The 28C 7453 only beats Intel’s best by a little so why is this a big deal? Didn’t SemiAccurate say Rome pummels Intel’s line and Milan was 20+% better? That theoretical leadership position isn’t exactly bolstered by the performance of the 7453.

Lets start out by saying that Milan does win outright, at least on the SPEC tests listed and probably a lot more too so there is that. More importantly the 7453 is a $1570 CPU, the it is up against is either the Cascade Lake (CSL) 8280 or the CSL-Refresh 6258R which cost $10,009 and $3950 respectively. Both are crippled though, for example the 8280 has memory artificially limited which Intel will sell back to you for a mere few $3000 or so.

If you just winced, it used to be $8000 before Intel had to accept reality and price things closer to sanity by dropping the top +$8000 tier. So in short the best case is that the Milan 7453 costs about half the still significantly crippled Xeon 6258R and about a sixth of the crippled in different ways Xeon 8280. The AMD offering is faster and has all features enabled on all SKUs. This isn’t a fight, the 28C Milan basically exists so hyperscalers can fit it into their offerings better, any other customer has better and much higher performance options.

So in the end Epyc 7xx3/Milan isn’t a game changer, just a solid performance improvement without any disruptive platform changes. Performance goes up significantly, price/performance gets measurably better, energy use stays the same, security improves, features are added, and SKUs are tuned to make life easier for the big players. In short there are no real down sides to Milan. Your homework now is to go over the list in this paragraph and figure out how many of these things apply to Ice Lake.S|A

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Charlie Demerjian

Roving engine of chaos and snide remarks at SemiAccurate
Charlie Demerjian is the founder of Stone Arch Networking Services and is a technology news site; addressing hardware design, software selection, customization, securing and maintenance, with over one million views per month. He is a technologist and analyst specializing in semiconductors, system and network architecture. As head writer of, he regularly advises writers, analysts, and industry executives on technical matters and long lead industry trends. Charlie is also available through Guidepoint and Mosaic. FullyAccurate